Manufacturing method of solid-state image sensor

ABSTRACT

A single crystal silicon layer is formed on a principal surface of a first wafer by epitaxial growth. A silicon oxide layer is formed on the single crystal silicon layer. Next, a defect layer is formed inside the single crystal silicon layer by ion implantation, and then, the second wafer is bonded to the silicon oxide layer on the first wafer. After that, an SOI wafer including the silicon oxide layer formed on the second wafer and the single crystal silicon layer formed on the silicon oxide layer is formed by separating the first wafer including the single crystal silicon layer from the second wafer including the single crystal silicon layer in the defect layer. Then, a photodiode is formed in the single crystal silicon layer. An interconnect layer is formed on a surface of the single crystal silicon layer which is opposite to the silicon oxide layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Divisional of application Ser. No. 13/220,079,filed Aug. 29, 2011, which is a continuation of PCT InternationalApplication PCT/JP2009/005509, filed on Oct. 21, 2009, which in turnclaims benefit of Japanese Patent Application No. 2009-066877, filed onMar. 18, 2009, the entire contents of each of which are incorporatedherein by reference.This application is a Reissue of U.S. patentapplication Ser. No. 14/061,750, filed on Oct. 23, 2013 now U.S. Pat.No. 9,018,031, which is a divisional application of U.S. patentapplication Ser. No. 13/220,079, filed on Aug. 29, 2011, which is acontinuation of PCT International Application PCT/JP2009/005509, filedon Oct. 21, 2009, which in turn claims benefit of Japanese PatentApplication No. 2009-066877, filed on Mar. 18, 2009, the entire contentsof each of which are incorporated herein by reference.

BACKGROUND

The present disclosure relates to solid-state image sensors andmanufacturing methods of the sensors, and more particularly tosolid-state image sensors using silicon-on-insulator (SOI) substratesand manufacturing methods of the sensors.

Solid-state image sensors such as charge coupled devices (CCDs), CMOSimage sensors, etc., are generally used for digital cameras, videocameras, etc. In recent years, with an improvement in solid-state imagesensors, high-definition images can be obtained by a solid-state imagesensor with highly dense pixels.

A conventional solid-state image sensor includes a transfer gate, aphotoelectric conversion element, a MOS transistor, variousinterconnects, etc. on a semiconductor substrate. However, alight-receiving region of a photoelectric conversion element needs to beprovided avoiding the transfer gate, the MOS transistor, theinterconnects, etc. There is thus the problem that the aperture ratio ofthe light-receiving region reduces with a reduced pixel size due toreduction in the area of the semiconductor substrate and an increase inthe number of pixels.

Thus, in recent years, increasing attention has been given to asolid-state image sensor of back surface irradiation including atransfer gate, a MOS transistors, and an interconnect layer on a first(front) surface of a semiconductor substrate, and a photoelectricconversion element on a second (back) surface so that the back surfaceserves as a light-receiving region.

A substrate of a solid-state image sensor of back surface irradiationneeds to be thinned to a thickness of 3-10 μm. As a means of thinning,polishing or etching of a conventional silicon substrate from a backsurface is considered, but the means is less controllable in uniformlyreducing the thickness of an initial substrate, which is usually 500 μm,to 10 μm or less.

For example, Japanese Translation of PCT International Application No.2008-514011 shows a manufacturing method of a solid-state image sensorof back surface irradiation using an SOI wafer including a singlecrystal silicon layer on a silicon oxide layer.

In the manufacturing method shown in Japanese Translation of PCTInternational Application No. 2008-514011, the SOI wafer including thesilicon oxide layer formed on a base wafer, and the single crystalsilicon layer formed on the silicon oxide layer is used. The methodincludes forming a photoelectric conversion element on the singlecrystal silicon layer with a light-receiving section facing the siliconoxide layer of the single crystal silicon layer, forming an interconnectlayer on a surface of the single crystal silicon layer which is oppositeto the surface closer to the silicon oxide layer, and selectivelyremoving the base wafer under the silicon oxide layer.

As representative manufacturing methods of an SOI wafer, roughly twotypes of separation by implanted oxygen (SIMOX) and bonding are known.The SIMOX is a manufacturing method of an SOI wafer utilizing thefeature that a silicon oxide layer is formed inside a silicon substrateand a recrystallized silicon layer is formed near the surface of thesilicon substrate by ion-implanting highly concentrated oxygen into thesilicon substrate with highly accelerated energy and performing heattreatment. This method accurately controls the depth for ionimplantation, thereby providing excellent uniformity of the thickness ofthe recrystallized silicon layer formed near the surface of the siliconsubstrate. However, a non-single crystal silicon oxide layer occurs inthe heat treatment, and the recrystallized silicon layer is formed onthe non-single crystal silicon oxide layer, thereby causing a largenumber of crystal defects in the recrystallized silicon layer. Althoughconsiderable efforts have been made to reduce the crystal defects, theproblem is not yet overcome, since the mechanism of occurrence of thedefects is intrinsic. The defects are considered difficult to overcomein the future.

Then, wafer bonding was suggested. A Unibond technique (Smart Cut(registered trademark)) is practically the current mainstream.

In the Unibond technique, a silicon oxide film is formed on the surfaceof a silicon substrate, hydrogen ions are implanted via the formedsilicon oxide film, and then the silicon oxide film of the siliconsubstrate is bonded to a base wafer (supporting substrate). After that,heat treatment is performed and the silicon substrate is separated inthe implanted position, thereby providing a method (hydrogen ionimplantation separation) of forming an SOI wafer. This technique isshown in, e.g., Japanese Patent No. 2959704, or Japanese Patent No.3385972.

As the method of separating the hydrogen ions, a silicon oxide film isformed on at least one of two silicon wafers. Hydrogen ions or noble gasions are implanted from above a first silicon wafer, thereby forming adefect layer (a sealing layer) inside the silicon wafer. Then, thesilicon wafer is adhered to the other silicon wafer via the siliconoxide film and heat treatment (separation heat treatment) is performedto separate one of the wafers to be a thin film using the defect layeras a surface to be cleaved (surface to be separated). With further heattreatment (bonding heat treatment) is performed to strengthen thebonding, thereby forming an SOI wafer.

SUMMARY

A silicon wafer used in manufacturing an SOI wafer is usually formed byCzochralski (CZ) growth. In the CZ growth, massive polycrystallinesilicon is put into a crucible made of quartz and melted by resistanceheating in an argon atmosphere. A silicon ingot comes into contact withsingle crystal silicon as a seed and is pulled up while graduallyrotating to manufacture the silicon ingot. The resistivity of silicon iscontrolled by the concentration of a dopant, but the resistivity in theaxial direction and the in-plane direction is difficult to uniform.Variations in concentric resistivity, oxygen concentration, etc. causedby the pull-up of the silicon wafer produced by the CZ growth arereferred to as “swirls.” FIG. 9 is a schematic view of a swirlrepresenting the magnitude of resistivity by concentration. Even withsuch a problem, single crystals can be formed with a great opening sizeof 300 mm or more depending on a pull-up machine, and thus, wafers witha great opening size used in manufacture of semiconductors in recentyears are all produced by the CZ growth.

SOI wafers manufactured by hydrogen ion implantation separation usingsilicon wafers produced by the CZ growth are in practical use mainly inlogic LSI manufactures. In usually manufactured SOI wafers, variationsin resistivity caused by the CZ growth are not problematic.

A manufacturing method of a solid-state image sensor of back surfaceirradiation using an SOI wafer, which is formed by hydrogen ionimplantation separation using a silicon wafer produced by CZ growth as amaterial, will be described below.

FIGS. 10A-10E and 11A-11E are cross-sectional views illustrating amanufacturing method of a solid-state image sensor of back surfaceirradiation using a conventional SOI wafer.

As shown in FIG. 10A, a bond wafer 5 made of single crystal silicon isprepared. The bond wafer 5 is made of single crystal silicon produced byCZ growth. P-type impurities are implanted into the bond wafer 5 so thatthe bond wafer 5 will be a p-well 6 of a completed solid-state imagesensor 3 shown in FIG. 11E. The bond wafer 5 is shown in the figure sothat the principal surface faces downwards.

Then, as shown in FIG. 10B, the bond wafer 5 is thermally oxidized toform a silicon oxide layer 7. While only the silicon oxide layer 7 onthe principal surface is shown in the figure, silicon oxide films areactually formed on the back and side surfaces as well.

Next, as shown in FIG. 10C, hydrogen ions are implanted from theprincipal surface of the bond wafer 5. Accelerated energy for implantingthe hydrogen ions is controlled to adjust the depth of a defect layer 8,which is caused by the hydrogen ion implantation, from the principalsurface of the bond wafer 5. This determines the thickness of a singlecrystal silicon layer 9 being an upper layer when an SOI wafer 1 iscompleted, which will be described later with reference to FIG. 11A.

Then, as shown in FIG. 10D, the surfaces of the bond wafer 5 and a basewafer 2 for maintaining the strength of the SOI wafer 1 are cleaned andbonded. The base wafer 2 is made of single crystal silicon produced byCZ growth.

After that, as shown in FIG. 10E, the base wafer 2 and the bond wafer 5are separated from the back surface, thereby separating part of the bondwafer 5 from the base wafer 2 in the defect layer 8. The part of thebond wafer 5 separated from the base wafer 2 is returned to theoxidation shown in FIG. 10B, and may be reused in manufacture of anotherSOI wafer.

Then, heat treatment is performed to strengthen the bonding of thebonded surfaces. Normally, it is said that bonding of bonded surfaces isstrengthen by heat treatment at a temperature of 1000° C. A method oflowering the temperature of the heat treatment by pretreatment withplasma, etc. is also considered.

With the above-described processes, as shown in FIG. 11A, the SOI wafer1 is completed, which includes the base wafer 2, the silicon oxide layer7, and the single crystal silicon layer 9.

FIG. 11B illustrates forming photodiodes 4 and drains 11 in the singlecrystal silicon layer 9 which is the uppermost layer of the SOI wafer 1,and forming read-out gates 10 and interconnects 12 on the single crystalsilicon layer 9 to form a solid-state MOS image sensor. In the case of asolid-state CCD image sensor, photodiodes, charge transfer sections,gate electrodes and interconnects are used instead. The photodiodes 4are formed by ion-implanting impurities such as arsenic (As), properties(P), etc. into a p-type substrate.

Then, as shown in FIG. 11C, the base wafer 2 is removed from the SOIwafer 1. When the base wafer 2 is made of single crystal silicon, it canbe easily removed by etching with an alkali solution. The intermediatesilicon oxide layer 7 is not etched with the alkali solution, it can bethus processed with thickness accuracy equal to that in manufacturingthe SOI wafer 1. This is the greatest advantage of using the SOI wafer1. At this time, when removing the base wafer 2 from the entire surfaceof the SOI wafer 1, the strength of the wafer is insufficient, and thus,an extra support wafer for reinforcement is to be bonded on the frontsurface provided with the interconnects 12, etc. The support wafer ishowever, not shown in the figure.

After that, as shown in FIG. 11D, boron (B⁺) ions are implanted from thesurface provided with the silicon oxide layer 7 to form a p⁺ typedepletion barrier layer 13 near the interface in the single crystalsilicon layer 9 between the single crystal silicon layer 9 and thesilicon oxide layer 7. The depletion barrier layer 13 blocks spread ofthe depletion layers of the photodiodes 4 to the interface with thesilicon oxide film and prevents noise electrons generated at interfacestates from being accumulated at the photodiodes 4 and becoming darksignals.

Next, as shown in FIG. 11E, color filters 14 and on-chip microlenses 15are formed on the silicon oxide layer 7 being the back surface of theSOI wafer 1. Then, the solid-state image sensor 3 of back surfaceirradiation is completed.

The manufacturing method of the solid-state image sensor of back surfaceirradiation using the conventional SOI wafer is excellent in uniformlyand controllably thinning the silicon wafer. However, slight variationsin the resistivity of the substrate influence characteristics of theindividual photodiodes, and lead to variations in sensitivity and theamount of saturated signals. As a result, fixed pattern noise occurs inan obtained image due to a swirl shown in FIG. 12.

In view of the problem, it is an objective of the present disclosure toreduce variations in resistivity of a substrate and to reducedegradation in the quality of an obtained image in a solid-state imagesensor using an SOI substrate.

In order to achieve the objective, the present disclosure provides amanufacturing method of a solid-state image sensor implemented by astructure using an SOI wafer made of single crystal silicon formed byepitaxial growth.

Specifically, a manufacturing method of a first solid-state image sensoraccording to the present disclosure includes forming a single crystalsilicon layer on a principal surface of a first wafer by epitaxialgrowth; forming a silicon oxide layer on the single crystal siliconlayer; forming a defect layer inside the single crystal silicon layer byion implantation; bonding the second wafer to the silicon oxide layer onthe first wafer; forming an SOI wafer including the silicon oxide layerformed on the second wafer and the single crystal silicon layer formedon the silicon oxide layer by separating the first wafer including thesingle crystal silicon layer from the second wafer including the singlecrystal silicon layer in the defect layer; forming a photodiode in thesingle crystal silicon layer; and forming an interconnect layerincluding a photodiode charge read-out structure on a surface of thesingle crystal silicon layer which is opposite to the silicon oxidelayer.

In the manufacturing method of the first solid-state image sensoraccording to the present disclosure, the first solid-state image sensoraccording to the present disclosure does not include single crystalsilicon produced by CZ growth, which inevitably has concentricvariations in impurity concentration. This prevents fixed pattern noiseoccurring in the solid-state image sensor manufactured by a conventionalmanufacturing method. This enables manufacture of a solid-state imagesensor with reduced degradation in the quality of an obtained image.

The manufacturing method of the first solid-state image sensor accordingto the present disclosure may further include, after forming theinterconnect layer, selectively etching part of or the entire secondwafer with respect to the silicon oxide layer. In forming thephotodiode, the light-receiving section of the photodiode is formed toface the silicon oxide layer.

A manufacturing method of a second solid-state image sensor according tothe present disclosure includes forming a first single crystal siliconlayer on a principal surface of a first wafer by epitaxial growth;forming a silicon oxide layer on the first single crystal silicon layer;forming a defect layer inside the first single crystal silicon layer byion implantation; bonding the second wafer to the silicon oxide layer onthe first wafer; forming an SOI wafer including the silicon oxide layerformed on the second wafer and the first single crystal silicon layerformed on the silicon oxide layer by separating the first waferincluding the first single crystal silicon layer from the second waferincluding the first single crystal silicon layer in the defect layer;forming a second single crystal silicon layer on the first singlecrystal silicon layer by epitaxial growth; forming a photodiode in thefirst single crystal silicon layer or the second single crystal siliconlayer; and forming an interconnect layer including a photodiode chargeread-out structure on a surface of the second single crystal siliconlayer which is opposite to the first single crystal silicon layer.

In the manufacturing method of the second solid-state image sensoraccording to the present disclosure, the second solid-state image sensordoes not include single crystal silicon produced by CZ growth, whichinevitably has variations in impurity concentration. This prevents fixedpattern noise occurring in the solid-state image sensor manufactured bya conventional manufacturing method. This enables manufacture of asolid-state image sensor with reduced degradation in the quality of anobtained image. Furthermore, read-out gates, drains, interconnects, etc.of the solid-state image sensor can be formed on the surface of thedefect free second single crystal silicon layer, thereby furtherimproving the image quality of the solid-state image sensor.

The manufacturing method of the second solid-state image sensoraccording to the present disclosure may further include, after formingthe interconnect layer, selectively etching part of or the entire secondwafer with respect to the silicon oxide layer. In forming thephotodiode, the light-receiving section of the photodiode is formed toface the silicon oxide layer.

A manufacturing method of a third solid-state image sensor according tothe present disclosure includes forming a first single crystal siliconlayer having impurity concentration of 1×10¹⁷ cm⁻³ or more on aprincipal surface of a first wafer by epitaxial growth; forming asilicon oxide layer on the first single crystal silicon layer; forming adefect layer inside the first single crystal silicon layer by ionimplantation; bonding the second wafer to the silicon oxide layer on thefirst wafer; forming an SOI wafer including the silicon oxide layerformed on the second wafer and the first single crystal silicon layerformed on the silicon oxide layer by separating the first waferincluding the first single crystal silicon layer from the second waferincluding the first single crystal silicon layer in the defect layer;forming a second single crystal silicon layer having lower impurityconcentration than the first single crystal silicon layer on the firstsingle crystal silicon layer by epitaxial growth; forming a photodiodein the second single crystal silicon layer so that a light-receivingsection faces the silicon oxide layer; forming an interconnect layerincluding a photodiode charge read-out structure on a surface of thesecond single crystal silicon layer which is opposite to the firstsingle crystal silicon layer; and selectively etching part of or theentire second wafer with respect to the silicon oxide layer.

In the manufacturing method of the third solid-state image sensoraccording to the present disclosure, the third solid-state image sensordoes not include single crystal silicon produced by CZ growth, whichinevitably has variations in impurity concentration. This prevents fixedpattern noise occurring in the solid-state image sensor manufactured bya conventional manufacturing method. This enables manufacture of asolid-state image sensor with reduced degradation in the quality of anobtained image. Furthermore, read-out gates, drains, interconnects, etc.of the solid-state image sensor can be formed on the surface of thedefect free second single crystal silicon layer, thereby furtherimproving the image quality of the solid-state image sensor. There is noneed to form a depletion barrier layer by ion implantation to performactivation annealing after forming the read-out gates, interconnects,etc. Thus, a negative influence of heat treatment on the interconnects,etc. can be avoided.

In the manufacturing method of the third solid-state image sensoraccording to the present disclosure, the first single crystal siliconlayer is preferably of a first conductivity type. The second singlecrystal silicon layer is preferably of a second conductivity type. Thephotodiode is preferably of the second conductivity type.

In the manufacturing method of the third solid-state image sensoraccording to the present disclosure, the first single crystal siliconlayer may be of a first conductivity type. The second single crystalsilicon layer may be of a second conductivity type. The forming of thephotodiode may include forming a well of the first conductivity type inthe second single crystal silicon layer. The photodiode may be of thesecond conductivity type, and may be formed in the well.

A solid-state image sensor according to the present disclosure includesa plate-like single crystal silicon layer formed by epitaxial growth,and including a first surface and a second surface facing the firstsurface, an interconnect layer provided on the first surface of thesingle crystal silicon layer and including a photodiode charge read-outstructure; and a plurality of photodiodes formed in the single crystalsilicon layer so that light-receiving sections face the second surface.

The solid-state image sensor according to the present disclosure doesnot include single crystal silicon produced by CZ growth, whichinevitably has variations in impurity concentration. This prevents fixedpattern noise occurring in a conventional solid-state image sensor.

The solid-state image sensor according to the present disclosure mayfurther include an insulating film provided on the second surface of thesingle crystal silicon layer, and color filters provided on theinsulating film to correspond to the photodiodes.

The solid-state image sensor according to the present disclosure mayfurther include on-chip microlenses provided on the second surface ofthe single crystal silicon layer to correspond to the photodiodes.

The solid-state image sensor according to the present disclosure mayfurther include an insulating film provided on the second surface of thesingle crystal silicon layer; color filters provided on the insulatingfilm; and on-chip microlenses provided on the color filters tocorrespond to the photodiodes.

According to the solid-state image sensor and the manufacturing methodof the solid-state image sensor of the present disclosure, a solid-stateimage sensor does not include single crystal silicon produced by CZgrowth, which inevitably has variations in impurity concentration. As aresult, a solid-state image sensor is obtained, which is free from fixedpattern noise occurring in a solid-state image sensor manufactured by aconventional manufacturing method.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a solid-state image sensor accordingto a first embodiment of the present disclosure.

FIGS. 2A-2E are cross-sectional views illustrating a manufacturingmethod of the solid-state image sensor according to the first embodimentin order of steps.

FIGS. 3A-3F are cross-sectional views illustrating the manufacturingmethod of the solid-state image sensor according to the first embodimentin order of steps.

FIGS. 4A-4E are cross-sectional views illustrating a manufacturingmethod of the solid-state image sensor according to a second embodimentin order of steps.

FIGS. 5A-5G are cross-sectional views illustrating the manufacturingmethod of the solid-state image sensor according to the secondembodiment in order of steps.

FIGS. 6A-6E are cross-sectional views illustrating a manufacturingmethod of the solid-state image sensor according to a third embodimentin order of steps.

FIGS. 7A-7F are cross-sectional views illustrating the manufacturingmethod of the solid-state image sensor according to the third embodimentin order of steps.

FIG. 8 is a schematic view illustrating fixed pattern noise caused byvariations in activation of laser annealing.

FIG. 9 is a schematic view illustrating variations in impurityconcentration in a semiconductor wafer manufactured by conventional CZgrowth.

FIGS. 10A-10E are cross-sectional views illustrating a manufacturingmethod of a solid-state image sensor of back surface irradiation using aconventional SOI wafer in order of steps.

FIGS. 11A-11E are cross-sectional views illustrating a manufacturingmethod of a solid-state image sensor of back surface irradiation using aconventional SOI wafer in order of steps.

FIG. 12 is a schematic view illustrating fixed pattern noise of asolid-state image sensor of back surface irradiation using aconventional SOI wafer.

DETAILED DESCRIPTION First Embodiment

A solid-state image sensor according to a first embodiment of thepresent disclosure will be described hereinafter with reference toFIG. 1. FIG. 1 illustrates a cross-sectional structure of thesolid-state image sensor according to the first embodiment.

As shown in FIG. 1, the solid-state image sensor according to the firstembodiment includes a single crystal silicon layer 24 formed byepitaxial growth, and a silicon oxide layer 22 having a surface formedby heat treatment. Impurities are implanted into the single crystalsilicon layer 24 to have p-type conductivity for functioning as a p-well21.

The single crystal silicon layer 24 includes photodiodes 19 and drains26. Read-out gates 25 and interconnects 27 are formed on the singlecrystal silicon layer 24. An interlayer insulating film 34 is formed onthe single crystal silicon layer 24 to cover the read-out gates 25 andthe interconnects 27. The photodiodes 19 are formed by forming n-typeregions by implantation of ions such as arsenic, phosphorus, antimony,etc. The light-receiving sections of the photodiodes 19 are formed toface the silicon oxide layer 22.

For example, boron (B⁺) ions are implanted from the surface providedwith the silicon oxide layer 22, thereby forming the p⁺ type depletionbarrier layer 28 under the single crystal silicon layer 24. The impurityconcentration of the depletion barrier layer 28 varies depending on theimpurity concentration of the photodiodes 19, and usually preferablyranges from 1×10¹⁷ cm⁻³ to 1×10¹⁹ cm⁻³ (both inclusive). This preventsspread of the depletion layers of the photodiodes 19 to the interfacewith the silicon oxide layer 22, and provides the advantage of reducingdark signals generated by accumulating noise electrons occurring in theinterface states at the photodiodes 19.

Color filters 29 are formed on the surface of the silicon oxide layer 22which is opposite to the single crystal silicon layer 24. On-chipmicrolenses 30 are formed on the color filters 29.

The solid-state image sensor according to this embodiment does notinclude single crystal silicon formed by Czochralski (CZ) growth, whichinevitably has concentric variations in impurity concentration. Thisprevents fixed pattern noise to improve image quality.

A manufacturing method of a solid-state image sensor including theabove-described structure will be described hereinafter with referenceto FIGS. 2A-2E and 3A-3F. FIGS. 2A-2E and 3A-3F illustrate amanufacturing method of the solid-state image sensor according to thefirst embodiment of the present disclosure in order of steps.

First, as shown in FIG. 2A, a bond wafer 20 made of single crystalsilicon is prepared. In this embodiment, the conductivity type and theimpurity concentration of the bond wafer 20 are not directly related tothe p-well 21 of the completed solid-state image sensor 18 shown in FIG.3F. In FIGS. 2A-2E and 3A-3F, the bond wafer 20 is shown with theprincipal surface facing downward. The bond wafer 20 may be made ofsingle crystal silicon produced by CZ growth.

Then, as shown in FIG. 2B, the single crystal silicon layer 24, intowhich p-type impurities are implanted, is disposed on the principalsurface of the bond wafer 20 by epitaxial growth. In this embodiment,the single crystal silicon layer 24 needs to have a thickness greaterthan the thickness of the surface on which a solid-state image elementis eventually formed. Since a solid-state image sensor using visiblelight with sensitivity needs to include a substrate with a thicknessranging from several micrometers to ten micrometers, the single crystalsilicon layer 24 by epitaxial growth needs to have the depositionthickness ranging from several micrometers to ten micrometers.

Next, as shown in FIG. 2C, the bond wafer 20 is thermally oxidized toform the silicon oxide layer 22. While only the front (lower) surface ofthe formed silicon oxide layer 22 is shown in the figure, the siliconoxide layer 22 is actually formed on the back and side surfaces of thebond wafer 20 as well.

After that, as shown in FIG. 2D, hydrogen ions are implanted to thesingle crystal silicon layer 24 from the silicon oxide layer 22 to forma defect layer 23 inside the single crystal silicon layer 24. Afterbonding the bond wafer 20 to a base wafer 17, the bond wafer 20 isseparated along the defect layer 23. Thus, accelerated energy inimplanting the hydrogen ions is controlled to adjust the depth of theion implantation, thereby determining the thickness of the singlecrystal silicon layer 24 in the silicon-on-insulator (SOI) wafer.Therefore, in this embodiment, the depth of the defect layer 23eventually becomes the thickness of the single crystal silicon formingthe solid-state image sensor 18. When the solid-state image sensor 18 ofback surface irradiation is formed, it has a thickness ranging fromabout several micrometers to about ten micrometers as described above.Since the deposition thickness of the single crystal silicon layer 24 bythe epitaxial growth shown in FIG. 2B is larger than the thickness ofthe single crystal silicon forming the solid-state image sensor 18, thedefect layer 23 formed by implanting the hydrogen ions is provided inthe single crystal silicon layer 24 formed by epitaxial growth.

Then, as shown in FIG. 2E, a base wafer 17 for maintaining the strengthof an SOI wafer 16 to be completed in FIG. 3B. The surfaces of theprepared base wafer 17 and the single crystal silicon layer 24 arecleaned, and then, the surfaces of the base wafer 17 and the singlecrystal silicon layer 24 are bonded. At this time, atomic force at thesurfaces promotes the bonding only by softly pushing the base wafer 17and the bond wafer 20, on which the single crystal silicon layer 24 isdeposited, since the surfaces are sufficiently flat. The cleaning aimsnot only to remove contaminated materials, particles, etc. and to makethe surfaces hydrophilic to improve bonding effects. In this embodiment,the base wafer 17 may be made of single crystal silicon produced by CZgrowth. While the base wafer 17 is shown as if it is thinner than thebond wafer 20 for convenience, the base wafer 17 needs to have athickness for maintaining the strength of the SOI wafer 16. Therefore,when the diameter is 200 mm or more, a thickness of 500 μm is usuallyneeded. The bond wafer 20 also needs to have the same degree ofthickness as the base wafer 17 to be subjected to the steps to bondingof the bond wafer 20 to the base wafer 17.

After that, as shown in FIG. 3A, when the base wafer 17 and the bondwafer 20 are separated from the back surface, the single crystal siliconlayer 24 is separated in the defect layer 23. Part of the bond wafer 20and the single crystal silicon layer 24 eparated from the base wafer 17may be returned to the epitaxial growth shown in FIG. 2B and reused inmanufacture of another SOI wafer.

Then, heat treatment is performed to strengthen the bonding of bondedsurfaces. The temperature of the heat treatment is 400° C. or more inview of the bonding strength, and is preferably about 1000° C.

With the above-described steps, the SOI wafer 16 including the basewafer 17, the silicon oxide layer 22, and the single crystal siliconlayer 24 is completed as shown in FIG. 3B. In the SOI wafer 16 formed inthis embodiment, the entire single crystal silicon layer 24 is formed byepitaxial growth. Thus, the SOI wafer 16 formed in this embodiment hasfewer variations in impurity concentration than a conventional singlecrystal silicon layer produced by CZ growth.

Next, as shown in FIG. 3C, the photodiodes 19 and the drains 26 areformed in the single crystal silicon layer 24, and the read-out gates 25and the interconnects 27 are formed on the single crystal silicon layer24 to form a solid-state MOS image sensor. In the case of a solid-statecharge coupled device (CCD) image sensor, photodiodes, charge transfersections, gate electrodes and interconnects are used instead. In thisembodiment, the photodiodes 19 are formed in the p-type single crystalsilicon layer 24. Thus, in forming the photodiodes 19, impurities suchas arsenic, phosphorus, antimony, etc. are ion-implanted to form ann-type region. The interlayer insulating film 34 is formed on the singlecrystal silicon layer 24 to cover the read-out gates 25 and theinterconnects 27.

Note that, in this embodiment, in FIG. 2B, the single crystal siliconlayer 24 having p-type conductivity is formed by epitaxial growth. Thesingle crystal silicon layer 24 may be of an n-type, and the p-well 21may be formed by ion implantation etc. in the step shown in FIG. 3C toform the photodiodes 19 etc. in the formed p-well 21.

Then, as shown in FIG. 3D, the base wafer 17 is removed. It is efficientto perform etching with an alkali solution after removing a large partof the base wafer 17 by polishing, dry etching, etc. However, onlyetching with an alkali solution suffices. Since the base wafer 17 ismade of single crystal silicon, removal is facilitated by etching withan alkali solution. Furthermore, the intermediate silicon oxide layer 22is not etched by an alkali solution, and serves as an etching stopper.This enables processing of thinning films with high accuracy in the casewhere the thickness of the SOI wafer 16 is determined mainly by thedepth of hydrogen ion implantation. The greatest advantage of using theSOI wafer 16 is that the thickness accuracy is dramatically high ascompared to the case where a single layer single crystal silicon waferwith a thickness of 500 μm or more is processed to a thickness of about10 μm by combining polishing and etching. Removal of the base wafer 17may be limited to the light-receiving region of the solid-state imagesensor 18 using a masking step. When the base wafer 17 is removed fromthe entire surface of the SOI wafer 16, the strength of the entire waferis insufficient. Thus, the SOI wafer 16 is preferably strengthen bybonding a quartz wafer etc. as a support wafer on the front surfaceprovided with the interconnects 27 etc. in advance. Note that thesupport wafer is not shown in the figure. In this embodiment, an examplehas been described where only the base wafer 17 is removed. Even whenselectively removing the silicon oxide layer 22 by etching with acidafter removing the base wafer 17 with an alkali solution etc., theprocessing accuracy of the thickness is not different and the advantageof using the SOI wafer 16 can be provided.

Then, as shown in FIG. 3E, boron ions are implanted from the surfaceprovided with the silicon oxide layer 22 to form a p⁺ type depletionbarrier layer 28 near the interface in the single crystal silicon layer24 between the single crystal silicon layer 24 and the silicon oxidelayer 22. The concentration of the depletion barrier layer 28 variesdepending on the impurity concentration of the photodiodes 19, butusually preferably ranges from 1×10¹⁷ cm⁻³ to 1×10¹⁹ cm⁻³ (bothinclusive). This blocks spread of the depletion layers of thephotodiodes 19 to the interface with the silicon oxide film and preventsnoise electrons generated at interface states from being accumulated atthe photodiodes 19 and becoming dark signals. Note that, even when thestep is omitted, basic functions as an image sensor can be obtainedalthough image quality is degraded.

After that, as shown in FIG. 3F, color filters 29 and on-chipmicrolenses 30 are formed on the silicon oxide layer 22 as necessary. Asa result, the solid-state image sensor 18 of back surface irradiation iscompleted, which is formed of the single crystal silicon layer 24 byepitaxial growth.

In the manufacturing method of the solid-state image sensor according tothis embodiment, the solid-state image sensor 18 does not include singlecrystal silicon produced by CZ growth, which inevitably has concentricvariations in impurity concentration. As a result, the solid-state imagesensor free from fixed pattern noise as shown in FIG. 12 can bemanufactured.

While in this embodiment, the solid-state image sensor of back surfaceirradiation has been described, a conventional solid-state image sensorof front surface irradiation can be manufactured similarly using an SOIwafer. Thinning a light-receiving region in a solid-state image sensorof front surface irradiation is advantageous in for example, allowingspecific short wavelength to have sensitivity, and utilizing transmittedlight of the solid-state image sensor for some purposes. In this case,the depletion barrier layer 28 shown in FIG. 3E needs to be formed byimplanting boron ions to the surface of the single crystal silicon layer24 which is opposite to the above-described surface. The formation isperformed in the step shown in FIG. 3D.

While in this embodiment, a manufacturing method has been describedusing a solid-state MOS image sensor as an example, a similarmanufacturing method is applicable using an SOI wafer in a solid-stateCCD image sensor.

While in this embodiment, an example has been described where thephotodiodes 19 are formed in the p-well 21, the manufacturing method ofthe solid-state image sensor of the present disclosure is applicablewith a well of the other conductivity type.

While in this embodiment, an example has been described where hydrogenion implantation separation is used, similar advantages can be obtainedby other separation methods used in Uni Bond, for example, ionimplantation separation using argon ions etc. other than hydrogen ions.

Second Embodiment

A manufacturing method of a solid-state image sensor according to asecond embodiment will be described hereinafter with reference to FIGS.4A-4E and 5A-5G.

FIGS. 4A-4E and 5A-5G illustrate a manufacturing method of thesolid-state image sensor according to the second embodiment of thepresent disclosure in order of steps.

The steps shown in FIGS. 4A-5B are similar to the steps of the firstembodiment shown in FIGS. 2A-3B, and explanation thereof will beomitted. Note that the single crystal silicon layer 24 of the firstembodiment corresponds to a first single crystal silicon layer 32 inthis embodiment.

As shown in FIG. 5C, a second single crystal silicon layer 31 isdeposited on the first single crystal silicon layer 32 by epitaxialgrowth. P-type impurities are implanted into the second single crystalsilicon layer 31. As a result, the sum of the thickness of the seperatedfirst single crystal silicon layer 32 and the thickness of the secondsingle crystal silicon layer 31 is the substrate thickness of thesolid-state image sensor 18 shown in FIG. 5G. As described above, thesubstrate needs to have a thickness ranging from about severalmicrometers to about ten micrometers in a solid-state image sensor ofback surface irradiation. Therefore, where the depth of the defect layer23 in the first single crystal silicon layer 32 is d1, and the thicknessof the deposited second single crystal silicon layer 31 in FIG. 5C isd2, the sum of d1 and d2 needs to be equal to the substrate thickness ofthe solid-state image sensor 18.

Then, as shown in FIG. 5D, photodiodes 19 and drains 26 are formed onthe second single crystal silicon layer 31, and read-out gates 25 andinterconnects 27 are formed on the second single crystal silicon layer31 to form a solid-state MOS image sensor. In the case of a solid-stateCCD image sensor, photodiodes, charge transfer sections, gate electrodesand interconnects are used instead. In this embodiment, since thephotodiodes 19 are formed in the second single crystal silicon layer 31,impurities such as arsenic, phosphorus, antimony, etc. are ion-implantedin forming the photodiodes 19 to form an n-type region. Furthermore, theinterlayer insulating film 34 is formed on the single crystal siliconlayer 24 to cover over the read-out gates 25 and the interconnects 27.

Note that, in this embodiment, the second single crystal silicon layer31 of n-type conductivity may be formed by epitaxial growth, a p-well 21may be formed by ion implantation etc., and the photodiodes 19 etc. maybe formed in the p-well 21.

Next, as shown in FIG. 5E, the base wafer 17 is removed. It is efficientto perform etching with an alkali solution after removing a large partof the base wafer 17 by polishing, dry etching, etc. However, onlyetching with an alkali solution suffices. Since the base wafer 17 ismade of single crystal silicon, removal is facilitated by etching withan alkali solution. Furthermore, the intermediate silicon oxide layer 22is not etched by an alkali solution, and serves as an etching stopper.This enables processing of thinning films with high accuracy in the casewhere the thickness of the SOI wafer 16 is determined mainly by thedepth of hydrogen ion implantation. The greatest advantage of using theSOI wafer 16 is that the thickness accuracy is dramatically high ascompared to the case where a single layer single crystal silicon waferwith a thickness of 500 μm or more is processed to a thickness of about10 μm by combining polishing and etching. Removal of the base wafer 17may be limited to the light-receiving region of the solid-state imagesensor 18 using a masking step. When the base wafer 17 is removed fromthe entire surface of the SOI wafer 16, the strength of the entire waferis insufficient. Thus, the SOI wafer 16 is preferably strengthen bybonding a quartz wafer etc. as a support wafer on the front surfaceprovided with the interconnects 27 etc. in advance. Note that thesupport wafer is not shown in the figure. In this embodiment, an examplehas been described where only the base wafer 17 is removed. Even whenselectively removing the silicon oxide layer 22 by etching with acidafter removing the base wafer 17 with an alkali solution etc, theprocessing accuracy of the thickness is not different and the advantageof using the SOI wafer 16 can be provided.

Then, as shown in FIG. 5F, boron ions are implanted from the surfaceprovided with the silicon oxide layer 22 to form a p⁺ type depletionbarrier layer 28 near the interface in the first single crystal siliconlayer 32 between the first single crystal silicon layer 32 and thesilicon oxide layer 22. The concentration of the depletion barrier layer28 varies depending on the impurity concentration of the photodiodes 19,but usually preferably ranges from 1×10¹⁷ cm⁻³ to 1×10¹⁹ cm⁻³ (bothinclusive). This blocks spread of the depletion layers of thephotodiodes 19 to the interface with the silicon oxide layer 22 andprevents noise electrons generated at interface states from beingaccumulated at the photodiodes 19 and becoming dark signals. Note that,even when the step is omitted, basic functions as an image sensor can beobtained although image quality is degraded.

After that, as shown in FIG. 5G, color filters 29 and on-chipmicrolenses 30 are formed on the silicon oxide layer 22 as necessary. Asa result, the solid-state image sensor 18 of back surface irradiation iscompleted, which is formed of the first single crystal silicon layer 32and the second single crystal silicon layer 31 by epitaxial growth.

In the manufacturing method of the solid-state image sensor according tothis embodiment, the solid-state image sensor 18 does not include singlecrystal silicon produced by CZ growth, which inevitably has concentricvariations in impurity concentration. As a result, the solid-state imagesensor free from fixed pattern noise as shown in FIG. 12 can bemanufactured.

In this embodiment, the SOI wafer 16 is formed by hydrogen ionimplantation separation. A large part of the defect layer 23 due to ionimplantation remains on the surface separated by hydrogen ionimplantation. Thus, when the read-out gates 25, the drains 26, theinterconnects 27, etc. are formed on the surface separated by hydrogenion implantation; threshold voltages vary at the read-out gates 25 dueto an increase in interface states, dark outputs increase at the drains26, and an increase in contact resistance, variations in resistance,etc. at the interconnects 27, thereby causing degradation in imageequality due to an increase in noise etc. as a solid-state image sensor.In this embodiment, since the second single crystal silicon layer 31 isformed on a first single crystal silicon layer 32 including a surface onwhich a large part of the defect layer 23 remains. Thus, the read-outgates 25, the drains 26, the interconnects 27, etc. of the solid-stateimage sensor 18 can be formed on the surface of the defect free secondsingle crystal silicon layer 31. This improves image quality of theimage sensor. Furthermore, epitaxial growth of single crystal silicon isusually performed with silane source gas at a high temperature of 1000°C. Thus, hydrogen atoms ion-implanted from the silicon oxide layer 22into the first single crystal silicon layer 32 desorb to recover defectscaused by ion implantation.

The interface between the first single crystal silicon layer 32 and thesecond single crystal silicon layer 31 does not preferably exist in thedepletion layers of the photodiodes 19. The crystal defects remaininginside the photodiodes 19 are the source of dark currents, and causefixed pattern noise called “white defects.” In this embodiment, thethickness d1 of the separated first single crystal silicon layer 32 isset to be less than the thickness of the depletion barrier layer 28,thereby positioning the interface between the first single crystalsilicon layer 32 and the second single crystal silicon layer 31 insidethe depletion barrier layer 28. As a result, the structure is formed inwhich the interface between the first single crystal silicon layer 32and the second single crystal silicon layer 31 does not exist in thedepletion layers of the photodiodes 19. This structure further improvesimage quality of a solid-state image sensor.

While in this embodiment, an example has been described where hydrogenion implantation separation is used, similar advantages can be obtainedby other separation methods used in Uni Bond, for example, ionimplantation separation using argon ions etc. other than hydrogen ions.

Third Embodiment

A manufacturing method of a solid-state image sensor according to athird embodiment will be described hereinafter with reference to FIGS.6A-6E and 7A-7F.

FIGS. 6A-6E and 7A-7F illustrate a manufacturing method of thesolid-state image sensor according to the third embodiment of thepresent disclosure in order of steps. FIG. 8 is a schematic viewillustrating fixed pattern noise caused by variations in activation oflaser annealing.

The steps shown in FIGS. 6A-7E are similar to the steps of the secondembodiment shown in FIGS. 4A-5E, and explanation thereof will beomitted. Note that the first single crystal silicon layer 32 accordingto the second embodiment corresponds to a first depletion barrier singlecrystal silicon layer 33 in this embodiment. The first depletion barriersingle crystal silicon layer 33 is made of single crystal silicon havingthe same conductivity type as the depletion barrier layer 28 shown inFIG. 5F and impurity concentration equal to that of the depletionbarrier layer 28, i.e., having P⁺ type conductivity and impurityconcentration ranging from 1×10¹⁷ cm⁻³ to 1×10¹⁹ cm⁻³ (both inclusive).In the hydrogen ion implantation shown in FIG. 6D, the defect layer 23formed by hydrogen ion implantation has a depth equal to the thicknessof the depletion barrier layer 28 of the first and second embodiments,thereby allowing the first depletion barrier single crystal siliconlayer 33 to function as the depletion barrier layer 28 of the first andsecond embodiments. As a result, implantation of B⁺ ions is unnecessary.In this respect, this embodiment differs from the other embodiments.

Specifically, in this embodiment, after removing the base wafer 17 byetching shown in FIG. 7E, color filters 29, on-chip microlenses 30, etc.are formed the silicon oxide layer 22 as necessary, as shown in FIG. 7F.As a result, the solid-state image sensor 18 of back surface irradiationmade only of single crystal silicon by epitaxial growth is completed.

In order to allow the single crystal silicon to have electricalcharacteristics of a desired conductivity type by implantation ofimpurity ions such as boron, impurity atoms need to be located in stablepositions in the single crystal silicon by heat treatment generallycalled “activation annealing.” The activation annealing needs to beperformed by heat treatment at a temperature of 800° C. or more.However, when the read-out gates 25, the interconnects 27, etc. arealready formed, and particularly, when the interconnects 27 are made ofmetal such as aluminum or copper, the temperature applied to the entirewafer is considered based on the melting point of the interconnects 27.Heating at a temperature of 500° C. or more is difficult. As a result,only part of ion-implanted impurities can be activated.

As a method of solving this problem, heating called “laser annealing”can be used. In this method, a wafer is scanned with intense laser lightto heat the entire surface of the wafer. This locally heats one of thesurfaces of the wafer. There are however two problems in this method.The first problem is heat variations caused by scanning with laserlight. The maximum radius of laser light ranges from hundreds ofmicrometers to several millimeters, which is smaller than a solid-stateimage sensor and greater than a pixel size of the solid-state imagesensor. The heat variations caused by scanning of the laser light leadto variations in activation of impurities to cause variations inconductivity characteristics. This results in variations incharacteristics of individual pixels of the solid-state image sensor sothat fixed pattern noise caused by scanning variations of the laserlight shown in FIG. 8 occurs in the obtained image, thereby causingdegradation in image quality. The second problem is that the frontsurface (upper surface) of the wafer 16 has a high temperature, evenwhen the SOI wafer 16 is irradiated with laser light from the backsurface, since the thickness of the formation region of the photodiodes19 ranges from several micrometers to ten micrometers. In particular, asone of the advantages of a solid-state image sensor of back surfaceirradiation, the layout of the interconnects 27 at the front surface isnot limited by arrangement of pixels. However, when the wafer 16transmits part of laser light from the back surface and theinterconnects 27 reflects the part of laser light from the back surface,the temperature of the irradiated part with the reflected light risesmore than the other parts. This may cause variations in activation ofimpurities reflecting the layout of the interconnects 27, and fixedpattern noise of other types than the fixed pattern noise caused byscanning variations may be a concern. While the above-described problemsmay be solved, when laser annealing techniques with a short wavelengthis developed, the heat treatment in processing the back surface is anessential problem of a solid-state image sensor of back surfaceirradiation.

In the manufacturing method of the solid-state image sensor according tothis embodiment, there is no need to form the depletion barrier layer 28by ion implantation to perform activation annealing, after forming theread-out gates 25 and the interconnects 27. Therefore, fixed patternnoise caused by the activation annealing can be avoided.

When the impurity concentration of the first depletion barrier singlecrystal silicon layer 33 is sufficiently high, depletion does not occurat the interface between the first depletion barrier single crystalsilicon layer 33 and the second single crystal silicon layer 31, and theinterface is not included inside the photodiodes 19. As a result, whitedefects do not occur to obtain excellent image quality.

While in this embodiment, an example has been described where hydrogenion implantation separation is used, similar advantages can be obtainedby other separation methods used in Uni Bond, for example, ionimplantation separation using argon ions etc. other than hydrogen ions,similar to the first embodiment.

While in this embodiment, the second single crystal silicon layer 31 isof p-type conductivity and the photodiodes 19 is of n-type conductivity,the second single crystal silicon layer 31 may be of the n-typeconductivity. In this case, a p-well is formed in the second singlecrystal silicon layer 31 by ion implantation etc., and the photodiodes19 of n-type conductivity may be provided in the formed p-well.

The solid-state image sensor and the manufacturing method of thesolid-state image sensor according to the present disclosure provide asolid-state image sensor not including single crystal silicon producedby CZ growth which inevitably has concentric variations in impurityconcentration. This prevents fixed pattern noise, and thus, thesolid-state image sensor and the manufacturing method of the solid-stateimage sensor according to the present disclosure are particularly usefulas a solid-state image sensor and a manufacturing method etc. of thesolid-state image sensor using an SOI substrate.

What is claimed is:
 1. A manufacturing method of a solid-state imagesensor comprising: forming a first single crystal silicon layer having afirst impurity concentration on a principal surface of a first wafer byepitaxial growth; forming a silicon oxide layer on the first singlecrystal silicon layer; forming a defect layer inside the first singlecrystal silicon layer by ion implantation; bonding a second wafer to thesilicon oxide layer on the first wafer to form a combined wafer;formingseparating the combination wafer at the defect layer to form anSOI wafer including the silicon oxide layer that was formed on thesecond wafer and a portion of the first single crystal silicon layerthat was formed on the silicon oxide layer by separating the first waferincluding the first single crystal silicon layer from the second waferincluding the first single crystal silicon layer in the defect layer;forming a second single crystal silicon layer having a second impurityconcentration on the portion of the first single crystal silicon layerby epitaxial growth; forming a photodiode in the first single crystalsilicon layer or the second single crystal silicon layer; and forming aninterconnect layer including a photodiode charge read-out structure on asurface of the second single crystal silicon layer which is opposite tothe first single crystal silicon layer.
 2. The method of claim 1,further comprising after forming the interconnect layer, selectivelyetching part of or the entire etching the second wafer with respect tothe silicon oxide layer, wherein in forming the photodiode, thelight-receiving section of the photodiode is formed to face the siliconoxide layer.
 3. A manufacturing method of a solid-state image sensorcomprising: forming a first single crystal silicon layer having a firstimpurity concentration of 1×10¹⁷ cm⁻³ or more on a principal surface ofa first wafer by epitaxial growth; forming a silicon oxide layer on thefirst single crystal silicon layer; forming a defect layer inside thefirst single crystal silicon layer by ion implantation; bonding a secondwafer to the silicon oxide layer on the first wafer to form a combinedwafer; formingseparating the combination wafer at the defect layer toform an SOI wafer including the silicon oxide layer that was formed onthe second wafer and a portion of the first single crystal silicon layerthat was formed on the silicon oxide layer by separating the first waferincluding the first single crystal silicon layer from the second waferincluding the first single crystal silicon layer in the defect layer;forming a second single crystal silicon layer on the portion of thefirst single crystal silicon layer by epitaxial growth, the secondsingle crystal silicon layer having a second impurity concentrationlower than the first impurity concentration than the first singlecrystal silicon layer on the first single crystal silicon layer byepitaxial growth; forming a photodiode in the second single crystalsilicon layer so that a light-receiving section faces the silicon oxidelayer; forming an interconnect layer including a photodiode chargeread-out structure on a surface of the second single crystal siliconlayer which is opposite to the first single crystal silicon layer; andselectively etching part of or the entireetching the second wafer withrespect to the silicon oxide layer.
 4. The method of claim 3, whereinthe first single crystal silicon layer is of a first conductivity type,the second single crystal silicon layer is of a second conductivitytype, and the photodiode is of the second conductivity type.
 5. Themethod of claim 3, wherein the first single crystal silicon layer is ofa first conductivity type, the second single crystal silicon layer is ofa second conductivity type, the forming of the photodiode includesforming a well of the first conductivity type in the second singlecrystal silicon layer, and the photodiode is of the second conductivitytype, and is formed in the well.
 6. A manufacturing method of asolid-state image sensor comprising: forming a first single crystalsilicon layer having an impurity concentration on a principal surface ofa first wafer by epitaxial growth; forming a silicon oxide layer on thefirst single crystal silicon layer; forming a defect layer inside thefirst single crystal silicon layer by ion implantation; bonding a secondwafer to the silicon oxide layer on the first wafer to form a combinedwafer; separating the combination wafer at the defect layer to form anSOI wafer including the silicon oxide layer that was formed on thesecond wafer and a portion of the first single crystal silicon layerthat was formed on the silicon oxide layer; forming a well of a firstconductivity type in the portion of the first single crystal siliconlayer; forming a photodiode of a second conductivity type in the well ofthe first conductivity type so that a light-receiving section faces thesilicon oxide layer; forming an interconnect layer including aphotodiode charge read-out structure on a surface of the first singlecrystal silicon layer which is opposite to the first single crystalsilicon layer; and etching the second wafer with respect to the siliconoxide layer.